1. Field of the Invention
The present invention relates to a multiplex transmission system for converting data that have been encoded using 8B/10B encoding rules to data based on a transmission path standard after 64B/65B conversion and transmitting the data as well as to the converter used in this multiplex transmission system; and more particularly to a method of transmitting an alert for transmitting information regarding a problem to a client device on the receiving side when any type of problem occurs between a converter and a client device on the transmitting side.
2. Description of the Related Art
In recent years, Fibre Channel (FC) is being used as interface for forming connections between external storage devices as well as between storage devices and computers. Such Fibre Channel is a high-speed data communication technology that has been standardized by the American National Standards Institute (ANSI) and that has received widespread attention due to its potential for cutting costs and offering a real-time network environment.
However, the standards for transmission paths for realizing long-distance high-speed transmission do not necessarily assume the use of the Fibre Channel, and converters are therefore required for first multiplexing Fibre Channel signals and converting them to signals based on standards such as for Gigabit Ethernet (GbE) or Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH), transmitting the converted signals on a transmission path, and then converting the GbE or SONET/SDH signals to the original Fibre Channel signals on the receiving side.
However, 8B/10B block encoding is adopted in the physical layer of the above-described Fibre Channel. Details regarding 8B/10B block encoding are described in ANSI X3.230-1994 of the Fibre Channel Physical and Signaling Interface (FC-PH).
In 8B/10B block encoding, every 8 bits of data, for which 8 bits is the unit, are converted in accordance with prescribed encoding rules to 10-bit units of code. The original 8 bits is referred to as a “byte” and the 10 bits of code into which the bytes are converted is referred to as a “character”. In the present specification, these are referred to as “8B bytes” and “10B characters”.
According to 8B/10B encoding rules, the same bit value (“0” or “1”) does not continue for six or more times in the signals of 10B characters. In 8B/10B encoding rules, moreover, every 8B byte has two 10B characters determined in which the number of “0” and “1” are reciprocal. One of the two 10B characters is then selected according to the numbers of “0” and “1” in the preceding 10B character, as “Running Disparity”. A multiplicity of change points thus occurs in 10B character signals, and clocks and data are therefore easier to extract on the receiving side.
The 10B characters of 8B/10B block codes are defined such that 256 types of data codes and 12 types of control codes can be represented. Normally, data codes are represented by Dxx. y and control codes are represented by Kxx. y. Each data code corresponds to an 8B byte of the 256 8B bytes that are represented by 8 bits. Combinations of 10 bits that are not used as data codes are assigned to control codes. Control codes are used for transmitting control information for patterns for synchronizing characters or for link failures. By means of 8B/10 block encoding, not only are data transmitted transparently, but various control information is also transmitted.
FIG. 1 shows a multiplex transmission system in which FC devices, which are client devices that use this type of FC signal, are connected by way of a transmission path.
This multiplex transmission system realizes transmission and reception of data between FC device 101 and FC device 102, and, because the interposed transmission path is a GbE transmission path, the multiplex transmission system is further provided with converters 1201 and 1202. FC devices 101 and 102 are client devices that use Fibre Channel signals to transmit and receive data between converters 1201 and 1202.
Converter 1201 converts FC signals from FC device 101 to GbE signals and then sends the GbE signals onto the transmission path, and converts GbE signals that are received by way of the transmission path to FC signals and then sends the FC signals to FC device 101. Converter 1202 converts FC signals from FC device 102 to GbE signals and then sends the GbE signals onto the transmission path, and converts GbE signals that are received by way of the transmission path to FC signals and then sends the FC signals to FC device 102.
FIG. 2 shows the construction of converter 1201 that is shown in FIG. 1. As shown in FIG. 2, this converter 1201 is composed of O/E converter 131, S/P converter 32, FC-GbE converter 133, MAC (Media Access Control) address adder 34, MAC generator 35, 8B/10B encoder 36, P/S converter 37, E/O converter 38, O/E converter 41, S/P converter 42, 8B/10B decoder 43, MAC terminating unit 44, MAC address terminating unit 45, GbE-FC converter 146, P/S converter 47, and E/O converter 148.
O/E converter 131 converts optical signals from FC device 101 to electrical signals. S/P converter 32 converts serial electrical signals from O/E converter 131 to parallel signals. FC-GbE converter 133 converts parallel FC signals from S/P converter 32 to GbE signals. MAC address adder 34 performs processing for adding MAC addresses to GbE signals following the conversion by FC-GbE converter 133. MAC generator 35 performs MAC processing of data that have been given MAC address by MAC address adder 34. 8B/10B encoder 36 performs 8B/10B encoding of signals from MAC generator 35. P/S converter 37 converts the parallel signals that have been encoded by 8B/10B encoder 36 to serial signals. E/O converter 38 converts serial electrical signals from P/S converter 37 to optical signals.
O/E converter 41 converts optical signals that have been received from converter 1202 by way of the transmission path to electrical signals. S/P converter 42 converts the serial electrical signals from O/E converter 41 to parallel signals. 8B/10B decoder 43 performs 8B/10B decoding of signals from S/P converter 42. MAC terminating unit 44 performs MAC termination of signals that have been decoded by 8B/10B decoder 43. MAC address terminating unit 45 performs termination of the MAC addresses of data from MAC terminating unit 44. GbE-FC converter 146 performs processing to convert GbE signals from MAC address terminating unit 45 to FC signals. P/S converter 47 performs processing to convert parallel signals that have been converted by GbE-FC converter 146 to serial signals. E/O converter 148 performs processing to convert serial electrical signals from P/S converter 47 to optical signals.
FIG. 3 shows the construction of FC-GbE converter 133 that is shown in FIG. 2. As shown in FIG. 3, FC-GbE converter 133 is composed of 8B/10B decoder 51, word synchronization detector 152, 64 B/65B encoder 153, FIFO memory 54, FIFO control unit 55, and frame generator 56.
8B/10B decoder 51 performs 8B/10B decoding of the 10-bit parallel signals from S/P converter 32. Word synchronization detector 152 performs processing to detect word synchronization of the 9-bit data that has been subjected to 8B/10B decoding by 8B/10B decoder 51. 64B/65B encoder 153 performs 64B/65B encoding of data from word synchronization detector 152. FIFO memory 54 sequentially reads the data that have been 64B/65B encoded by 64B/65B encoder 153 and supplies these data as output. FIFO control unit 55 controls FIFO memory 54. Frame generator 56 cuts the data that have been supplied as output from FIFO memory 54 into frame units for every fixed length of data and transmits these data.
We next refer to FIG. 4, which shows the construction of GbE-FC converter 146 that is shown in FIG. 2. As shown in FIG. 4, GbE-FC converter 146 is composed of frame identifier 61, 64B/65B decoder 62, speed regulator 63, and 8B/10B encoder 164.
Frame identifier 61 identifies the frames of the data from MAC address terminating unit 45. 64B/65B decoder 62 performs 64B/65B decoding of signals from frame identifier 61. Speed regulator 63 performs regulation processing to match the transmission rate of signals that have been decoded by 64B/65B decoder 62 to the multiplexing hierarchy. 8B/10B encoder 164 performs 8B/10B encoding of data following the regulation of transmission rate by speed regulator 63.
In this case, 64B/65B code conversion is the conversion of eight 10B characters to 65-bits block-coded data. The 65-bits block-coded data that have undergone 64B/65B conversion are referred to as “64B/65B code”. Thus, in 64B/65B conversion, eight 10B characters are received as input and a 64B/65B code is supplied as output. This conversion reduces the number of bits from 80 to 65 and compresses the bandwidth to 81.25% (i.e., 65/80).
FIG. 5 shows the composition of a 64B/65B code. Referring to FIG. 5, the leading bit of the 64B/65B code is “0” only when all eight 10B characters that have been received are data codes. The leading bit is “1” when one or more control codes are included among the eight 10B characters. The 64 bits from the second to the 65th bit are divided by every eight bits into eight byte regions. The second bit to the ninth bit is the first byte, the tenth bit to the 17th bit is the second byte, and so on until the 58th bit to the 65th bit, which is the eighth byte.
Each byte region stores the 8-bit code of a converted 10B character. If a control code is included among the eight 10B characters that have been received as input, however, the order in which the 10B characters were received differs from the order in which the 8-bit codes of the converted 10B characters are stored. The control codes are stored together in order from the first byte, and the data codes are stored together following the control codes.
Regarding the codes that are to be stored, when the 10B characters are data codes, the 8B bytes that are decoded from these 10B characters are stored in the byte regions. When the 10B characters are control codes, 8-bit codes that are referred to as compression control codes are stored in the byte regions.
FIG. 6 shows the composition of compressed control code. Referring to FIG. 6, compressed control code is composed of three regions: a last control character”, a control character locator, and a control character indicator.
The first bit is the “last control character”. Control codes are stored together at the head of a 64B/65B code. When a control code succeeds in the next byte region, the “last control character” is “1”; and when that control code is the final one, the “last control character” is “0”.
The three bits from the second bit to the fourth bit are the control character locator. The location of the control codes among the eight 10B characters before transposition is indicated by binary data from “000 (=0)” to “111 (=7)”.
As an example, when the eight 10B characters are received as input in the order: D1, D2, D3, K1, D4, D5, D6, and K2 (where D indicates data codes and K indicates control codes), the data are stored in the first to eighth bytes of the 64B/65B code in the order: K1, K2, D1, D2, D3, D4, D5, and D6. Here, the “last control character” of K1 is “1” and the control character locator of K1 is “011 (=3)”. The “last control character” of K2 is “0”, and the control character locator of K2 is “111 (=7)”.
The four bits from the fifth bit to the eighth bit are the control character indicator. The control codes are codes that are represented by four bits.
The 64B/65B conversion that was described in the foregoing explanation causes a reduction of the number of bits of control codes and stores locators in 8-bit codes, whereby 10B character signals in which data code and control code are mixed are bandwidth compressed while maintaining transparency.
We next refer to the table of FIG. 7, which shows the relation between the 8B/10B control characters and 64B/65B control codes. FIG. 7 shows Table 8-1 in G. 7041 of the ITU-T recommendations and shows the relation between 8B/10B control characters and 64B/65B control codes.
When a problem occurs such as a break in the optical fiber cable between FC device 101 and converter 1201 in a prior-art multiplex transmission system of this type, data that have been transmitted by FC device 101 do not reach converter 1201. As a consequence, no data at all are transmitted from converter 1201 to converter 1202, and converter 1202, being unable to recognize that a problem has occurred such as a break in the optical fiber cable, transmits idle data to FC device 102. FC device 102 therefore determines that FC device 101 is simply not transmitting data.
Further, FC device 101 lacks any means for determining whether or not data have arrived at FC device 102, and therefore cannot detect that a problem has occurred and continues to transmit data despite the inability of FC device 102 to receive data.
In the example of the prior art that is shown in FIG. 1, the explanation presents a case in which the Fibre Channel is used as the interface standard between FC device 101 and converter 1201 and between FC device 102 and converter 1202, but standards other than the Fibre Channel include ESCON (Enterprise System CONnection), FICON (FIber CONnection), and DVB-ASI (Digital video Broadcasting-Asynchronous Serial Interface) as the interface standard between a computer and peripheral equipment. Similar problems occur even when employing interface standards other than the Fibre Channel. (ESCON and FICON are registered trademarks of IBM Corporation.)
Finally, in the example of the prior art that is shown in FIG. 1, a case was described in which the transmission path between converters 1201 and 1202 was GbE. However, when this transmission path is SONET, the use of an alert frame allows alert information to be transferred. However, the transfer of alert information necessitates the use of a special frame such as an alert frame, and this entails the problem that the transmission rate is consequently reduced.